1. Field of the Invention
This invention relates to memory cell redundancy in semiconductor memories.
2. State of the Art
Semiconductor memories generally include a multitude of memory cells arranged in rows and columns. Each memory cell is capable of storing digital information in the form of axe2x80x9c1xe2x80x9d or axe2x80x9c0xe2x80x9d bit. To write (i.e., store) a bit into a memory cell, a binary memory address having portions identifying the cell""s row (thexe2x80x9crow addressxe2x80x9d) and column (thexe2x80x9ccolumn addressxe2x80x9d) is provided to addressing circuitry in the semiconductor memory to activate the cell, and the bit is then supplied to the cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the cell is again activated using the cell""s memory address, and the bit is then output from the cell.
Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows or columns in the memory.
Conventionally, when a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell""s row address is permanently stored (typically in predecoded form) on a chip on which the semiconductor memory is fabricated by programming a non-volatile element (e.g., a group of fuses, anti-fuses, or FLASH memory cells) on the chip. Then, during normal operation of the semiconductor memory, if the memory""s addressing circuitry receives a memory address including a row address that corresponds to the row address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant row to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell""s row has the same row address, every cell in the failing cell""s row, both operative and failing, is replaced by a redundant memory cell in the redundant row.
Similarly, when a redundant column is used to repair the semiconductor memory, the failing cell""s column address is permanently stored (typically in pre-decoded form) on the chip by programming a non-volatile element on the chip. Then, during normal operation of the semiconductor memory, if the memory""s addressing circuitry receives a memory address including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell""s column has the same column address, every cell in the failing cell""s column, both operative and failing, is replaced by a redundant memory cell in the redundant column.
The process described above for repairing a semiconductor memory using redundant rows and columns is well known in the art, and is described in various forms in U.S. Pat. Nos. 4,459,685, 4,598,388, 4,601,019, 5,031,151, 5,257,229, 5,268,866, 5,270,976, 5,287,310, 5,355,340, 5,396,124, 5,422,850, 5,471,426, 5,502,674, 5,511,028, 5,544,106, 5,572,470, 5,572,471, and 5,583,463.
From the discussion of semiconductor memories thus far, it may appear that such memories comprise one large array of memory cells. This is true as far as other electronic devices are concerned, because such devices typically interact with a semiconductor memory as if it were a single array of memory cells arranged in as many rows and columns (referred to as xe2x80x9cglobalxe2x80x9d rows and columns) as are uniquely addressable by the memory""s row and column addresses.
However, internally, a modern semiconductor memory most often comprises multiple sub-arrays of memory cells, each containing xe2x80x9clocalxe2x80x9d rows and columns that are portions of the memory""s global rows and columns. Thus, for example, a 1 MB semiconductor memory addressable with 1,024 unique row and column addresses typically comprises four 256 KB sub-arrays, with each sub-array containing 512 local rows and columns, and each local row or column being one-half of a global row or column. As a result, each row address provided to the semiconductor memory uniquely addresses a global row comprised of two local rows in separate sub-arrays, and each column address provided to the memory then uniquely addresses a memory cell in one of the sub-arrays.
In such a semiconductor memory, because row addresses only uniquely address global rows, and do not uniquely address local rows, all local rows that make up a particular global row are activated when that global row is addressed. Similarly, all of the local rows that make up a global row are disabled and replaced with local redundant rows in their respective sub-arrays when a defective memory cell is found anywhere in the global row. Thus, for example, in the case of the 1 MB semiconductor memory discussed above, a defective memory cell in a local row of one sub-array is repaired by replacing the local row with a local redundant row in the sub-array. At the same time, however, a local row in an adjacent sub-array is also replaced with a local redundant row in that sub-array, despite the fact that the local row in the adjacent sub-array has no defects. This occurs because the addressing scheme of the semiconductor memory does not allow local rows to be uniquely addressed.
The conventional redundancy architecture described above is illustrated in FIG. 1. In normal operation, row decoders  less than 0 greater than  and  less than 1 greater than  activate selected wordline signals, and thereby activate selected rows within adjacent sub-arrays  less than 0 greater than  and  less than 1 greater than , in accordance with row addresses they receive. Thus, when a row address selects a particular global row comprised of local rows in the sub-arrays  less than 0 greater than  and  less than 1 greater than , row decoders  less than 0 greater than  and  less than 1 greater than  fire the wordline signals necessary to activate those local rows. Data is then written to, or read from, a memory cell in one of the sub-arrays  less than 0 greater than  and  less than 1 greater than  selected in accordance with a column address.
If a defective memory cell 10 is found in a local row LR_32 of the sub-array  less than 0 greater than , for example, then the row address of the global row with which the local row LR_32 is associated is stored in fuse banks 12. During subsequent memory operations, when a received row address matches the row address stored in the fuse banks 12, match signals output by the fuse banks 12 direct the row decoders  less than 0 greater than  and  less than 1 greater than  to not activate the local rows LR_32 in sub-arrays  less than 0 greater than  and  less than 1 greater than  and, instead, to activate redundant rows RR_0 in sub-arrays  less than 0 greater than  and  less than 1 greater than . As a result, the defective memory cell 10 is repaired.
It can be seen from this description that a few defective memory cells in either of the sub-arrays  less than 0 greater than  and  less than 1 greater than  will very quickly use up the redundant rows RR_0, RR_1, RR_2, and RR_3 available in the sub-arrays  less than 0 greater than  and  less than 1 greater than . Since redundant rows are typically formed at the edge of sub-arrays, a few repairs thus very quickly make such sub-arrays dependent on rows positioned right at their edges for normal operations. Since xe2x80x9cedgexe2x80x9d rows are more likely to have various fabrication errors and are more likely to be affected by the operations of peripheral circuitry, it is undesirable to have sub-arrays routinely dependent for normal operations on edge rows. This is especially true when the local row replaced (e.g., the local row LR_32 in the sub-array  less than 1 greater than ) has no defective memory cells, and yet is still replaced with a redundant row (e.g. the redundant row RR_0 of the sub-array  less than 1 greater than ) near the edge.
Therefore, there is a need in the art for a device and method for repairing a semiconductor memory that does not require the replacement of a good local row in a sub-array with a redundant row in that sub-array simply because a bad local row in an adjacent sub-array needs to be replaced with a redundant row in the adjacent sub-array. Also, there is a need for a device and method of conducting repairs that limits the use of redundant rows at the extreme edges of sub-arrays so that repairs can be more reliable.
An inventive redundancy architecture for repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for storing the row addresses of defective rows in sub-arrays of the memory. Such circuitry may include fuse banks, for example, or other non-volatile elements, such as anti-fuses or flash EEPROM cells. The circuitry also activates a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disables a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. Thus, the circuitry may also include row decoders associated with each of the sub-arrays.
By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the present invention allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation. Also, since the redundant row used for repairs in the one sub-array is typically nearest the center of the sub-array, the disabled redundant row in the adjacent sub-array is nearest the edge of that sub-array, because it is arranged in an order complementary to that of the redundant row used for repairs. As a result, the disabled redundant row acts as an edge buffer between the primary and redundant rows of the adjacent sub-array and peripheral circuitry.
In other embodiments of this invention, the redundancy architecture described above is incorporated into a semiconductor memory, a DRAM, a semiconductor wafer, and an electronic system.
In a redundancy method in accordance with this invention, row addresses of defective rows in a pair of sub-arrays in a semiconductor memory are stored. A redundant row in one of the sub-arrays is then activated in response to receiving a row address matching one of the stored defective row addresses. At the same time, activation of a redundant row arranged in the other of the sub-arrays in an order complementary to that of the activated redundant row is disabled.